ADVANCED COLLEGE OF
ENGINEERING AND MANAGEMENT
ER. SURENDRA DHAKAL
DEPARTMENT OF COMPUTER AND ELECTRONICS
ACEM, LALITPUR, NEPAL
27TH MARCH 2006
Initially, we would like to acknowledge our deep gratitude to Er. Surendra Dhakal for his suggestions and guidance for designing the microprocessor and preparing the report. We are very grateful to the Head of Department, Department of Computer and Electronics Engineering, Er. Pratik Lal Shrestha, for his valuable direction.
We would also like to extend our heartfelt thanks to our friend Mr. Rabin Bilas Pant [2059/BEX/122] and Mr. Smit Koirala [2059/BEX/131] without whose help, support and kind hospitality, it would have been difficult to complete our project.
Furthermore, we would like to thank our friends of Electronics and Communication Engineering and Computer Engineering. Moreover, we cannot close this chapter without expressing our thanks to every staffs and friends of our college who have encouraged us in the steps we have taken.
This project on MICROPROCESSOR DESIGN has been done for the partial fulfillment of the fourth year first part of Bachelor’s Degree in Electronics and Communication Engineering. We, somehow, have achieved a clear idea about microprocessor with the help of this project-work. During the project, we faced lot of difficulties. No doubt, by this project work, we have got a lot of experiences.
By completing the design, we have got the complete knowledge about the internal architecture of microprocessor and the performance of each complonent that we have used for the design. Different operations can be achieved from microprocessor; we have tried to accumulate most of them by writing the required instructions and their RTL.
The design was a sequential process. First of all, we wrote the instructions we needed and their RTL, then function table and signal generation and finally the block diagram of microprocessor were designed. The opcode are according to our instruction sheet.
Acknowledgement ..……... I
Abstract ..……... II
1 Introduction ……………….. 1
2 Objectives ……………….. 1
3 Requirements ……………….. 2
4 Control Unit ……………….. 5
5 Instruction Cycle ……………….. 9
6 Instruction Format ……………….. 10
7 Instruction Sheet ……………….. 11
8 Classification of Instructions ……………….. 12
9 Functional Table ……………….. 13
10 Signal Generation ……………….. 19
11 Function of Instructions ……………….. 23
12 Summary ……………….. 25
13 References ……………….. 25
14 Circuitry ……………….. 26
The internal logic design of the microprocessor, called its architecture, determines how and when various operations are performed by the microprocessor. The system bus provides paths for the flow of binary information (data and instructions). The internal logic design of the microprocessor consists of processor, memory and I/O modules, plus the interconnections among these major components.
The CPU consists of a control unit, registers, the arithmetic and logic unit, the instruction execution unit, and the interconnections among these components.
The control unit is that part of the processor that activates the various components of the processor.
The ALU is that part of the computer that actually performs arithmetic and logical operations on data. All of the other elements of the computer system – control unit, register, memory, I/O are there mainly to bring data into the ALU for it to process and then to take the results back out. Data are presented to the ALU in registers, and the result of an operation is stored in registers.
These registers are temporary storage locations within the processor that are connected by signal paths to the ALU. The ALU may also set flags as the result of an operation. The flag values are also stored in registers within the processor. The control unit provides signals that control the operation of the ALU and the movement of the data into and out of the ALU.
The major objective of this design is to achieve the complete knowledge about the internal architecture of microprocessor and the performance of each component that are used for design.
Memory → 256 bytes with address granularity 8 bits
Registers → A,B (Each 8-bit)
PC (Program Counter) → 8-bit
SP → 8-bit
Common Bus → 8-bit
Flag Registers → 8-bit
ALU → with two temporary i/p registers X&Y
Accumulator & o/p register Z
MAR → 8-bit
MBR → 8-bit
IR → 6-bit
SC → 4-bit
Decoders → Decoder (4x16)
Logic gates → OR, AND,NOT
Shift register → 8-bit
Stack memory → 64 bytes
ALU: Arithmetic and logic unit consists of two registers X &Y with signals S0, S1, S2 and the final result is loaded to register z. The combination of S0, S1, S2 are as follows:
So S1 S2 Output Operation
With Cin=0 With Cin=1 With Cin=0 With Cin=1
0 0 0 X+Y X+Y+1 Addition Addition with CY
0 1 0 X+ X-Y Subtraction with borrow Subtraction
1 0 0 X X+1 Transfer X Increment X
1 1 0 X-1 X Decrement X Transfer X
0 0 1
X ∩ Y AND
0 1 1 X U Y OR
1 0 1 X Y XOR
1 1 1 NOT
The memory used here is 256 bytes. The data in memory is of 1 byte granularity.
Some general purpose registers used are:
Accumulator(Ac) → 8 bits
Register A → 8 bits
Register B → 8 bits
Temporary registers X &Y → 8 bits each
Output register Z → 8 bits
Shift register (SR) → 8 bits
Some Control and Status registers used are
• Program Counter (PC) [8 bits]: holds the address of next instruction to be executed
• Memory Address Register (MAR) [8bits]: contains the address of a location in memory.
• Memory Buffer Register (MBR) [8bits]: contains the word of data to be written to memory or the word recently read.
• Instruction Register (IR): contains the instruction most recently fetched.
• Flag register: It holds the status of the result of the operation. It has four flags:
ii. Zero (Z)
iii. Parity (P)
iv. Carry (CY)
Our design has used only zero and carry flag. So their description is given below:
Zero (Z): The flag is set when any result of the arithmetic operation is zero.
Carry (CY): The flag is set when any operation generates the carry.
A register is a group of flip-flops with each flip-flop capable of storing one bit of information. An n-bit register has a group of n-flip flops and is capable of storing any binary information of n bits. In addition to the flip-flops, a register may have combinational gates that perform certain data-processing tasks. The flip–flop holds the binary information and the gates control when and how new information is transferred into the registers.
It is the circuitry that controls the flow of information through the processor and coordinates the activities of the other units within it. It is the brain within the brain as it controls what happen inside the processor which in turn controls the PC.
Types of Control Unit:
Hardwire Control Unit
Micro-programmed Control Unit
Hardwire Control Unit:
In this organization, the control logic is implemented with logic gates, flip flops, decoders and other circuits. It can be optimized to produce fast-mode of operation. It requires changes in wiring among various components if the design has to be modified or changed. So it is not flexible.
Micro-programmed Control Unit:
The Control logic, if programmed using micro-instructions, then it is called micro-program. A micro-program is a highly specialized computer program that allows one computer micro-architecture to emulate another.
Memory is an essential component of a microcomputer system; it stores binary instructions and data for the microprocessor. There are various types of memory which can be classified in two groups: prime (main) memory and storage memory.
The R/W memory is made of registers, and each register has a group of flip-flops or field effect transistors that store bits of information; these flip-flops are called memory cells. To communicate with memory, the MPU should be able to
Select the chip
Identify the register, and
Read from or write into the register
The Arithmetic and Logic Unit:
The ALU is the part of the computer that actually performs arithmetic and logic operations on the data. All of the elements of the computer system – control unit, register, memory, I/O – are there mainly to bring data into the ALU for it to process and then to take the results back out.
Data are presented to the ALU in registers and the result of an operation is stored in register. These registers are temporary storage locations within the processor that are connected by signal paths to the ALU. The ALU may also set flags on accordance to the result of an operation.
The two basic tasks performed by micro-programmed control unit are as follows:
• Microinstruction Sequencing: Get the next micro-instruction from the control memory.
• Microinstruction Execution: Generate the control signals needed to execute the micro instruction.
In designing a control unit, these tasks must be considered together, because both affect the format of the microinstruction and the timing of the control unit.
Instruction cycle is the processing required for a single instruction (i.e. No. of machine cycles required to process an instruction).
- Fetch: read the next instruction from memory into the CPU.
- Execute: interpret the op-code and perform the indicated operation.
It is a layout of instruction showing its constituent parts. An instruction has op-code and (or) operands. The operands are referenced by using any one of the addressing modes. Usually most instruction sets use more than one instruction format.
0 1 2 3 4 5 6 7
0 MOV A,B MVI A,data MVI B,data OUT 8-bit PORT ADDRESS IN 8-bit PORT ADDRESS HLT NOP ADD A,B
1 INR B DCR A DCR B ANA A ANA B ANI data ORA A ORA B
2 LDA 8-bit ADDRESS LDAX A LDAX B STAX A STAX B STA 8-bit ADDRESS CALL 8-bit ADDRESS RET
3 PUSH PSW XCHG A,B
8 9 A B C D E F
0 ADD A ADD B ADI data SUB A,B SUB A SUB B SUI data INR A
1 ORI data XRA A XRA B XRI data CMA JMP 8-BIT ADDRESS JC 8-BIT ADDRESS JZ 8-BIT ADDRESS
2 PUSH A PUSH B POP A RLA RRA RLC RRC CMP A,B
Classification of Instructions
According to function:
Data Transfer Arithmetic Logical Input/Output Transfer of Control
MVI A, data
MVI B, data
LDA 8-bit ADDRESS
STA 8- bit ADDRESS
XCHG A, B ADD A,B
CMP A,B OUT 8- bit ADDRESS
IN 8- bit ADDRES HLT
JMP 8- bit ADDRESS
JC 8- bit ADDRESS
JZ 8- bit ADDRESS
CALL 8- bit ADDRESS
According to Addressing Mode:
Direct Addressing Mode Stack Addressing Mode Immediate Addressing Mode Register Direct Addressing Mode Others
Out 8-bit PORT ADDRESS
In 8-bit PORT ADDRESS
JMP 8-bit ADDRESS
JC 8-bit ADDRESS
JZ 8-bit ADDRESS
LDA 8-bit ADDRESS
STA 8-bit ADDRESS
CALL 8-bit ADDRESS
RET PUSH A
POP PSW MVI A, data
MVI B, data
XRI data MOV A,B
XCHG A,B HLT
1. CLRSC = D0T3 + D1T5 + D2T5 + D3T6 + D4T6 + D6T3 + D7T6 + D8T6 + D9T6 + D10T8 + D11T6 + D13T6 + D14T8 + D15T5 + D16T5 + D17T5 + D18T5 + D19T6 + D20T6 + D21T8 + D22T6 + D23T6 + D24T8 + D25T6 + D26T6 + D27T8 + D28T6 + D29T5 + D30T5 + D31T5 + D32T7 + D33T5 + D34T5 + D35T5 + D36T5 + D37T7 + D38T6 + D39T4 + D40T4 + D41T4 + D42T4 + D43T5 + D44T5 + D45T5 + D46T5 + D47T6 + D48T6 + D49T5
= (D0 + D6)T3 + (D39 + D40 + D41+ D42)T4 + (D1+ D2 + D15 + D16 + D17 + D18 + D29 + D30 + D31+ D33 + D34 + D35 + D36 + D43 + D44 + D45 + D46 + D49)T5 + (D3 + D4 + D7 + D8 + D9 + D11+ D13 + D19 + D20 + D22 + D23 + D25 + D26 + D28 + D38 + D47 + D48)T6 + (D32 + D37)T7 + (D10 + D14 + D21+ D24 + D27)T8
2. PCin = D29T5 + D30T5*C + D31T5*Z + D38T6 + D39T3
= (D29 + D30*C + D31*Z)T5 + D38T6 + D39T3
3. PCout = T0 + D1T3 + D2T3 + D3T3 + D4T3 + D10T3 + D14T3 + D21T3 + D27T3 + D29T3 + D30T3 + D31T3 + D32T3 + D37T3 + D38T3 + D38T5
= T0 + (D1+ D2 + D3 + D4 + D10 + D14 + D21+ D24 + D27 + D29 + D30 + D31+ D32 + D37 + D38)T3 + D38T5
4. MARin = T0 + D1T3 + D2T3 + D3T3 + D3T5 + D4T3 + D4T5 + D10T3 + D14T3 + D21T3 + D24T3 + D27T3 + D29T3 + D30T3 + D31T3 + D32T3 + D32T5 + D33T3 + D34T3 + D35T3 + D36T3 + D37T3 + D37T5 + D38T3
= T0 + (D1+ D2 + D3 + D4 + D10 + D14 + D21+ D24 + D27 + D29 + D30 + D31+ D32 + D33 + D34 + D35 + D36 + D37 + D38)T3 + (D3 + D4 + D32 + D37)T5
5. MEMR =
T1+ D1T4 + D2T4 + D3T4 + D4T4 + D4T6 + D10T4 + D14T4 + D22T4 + D24T4 + D27T4 + D29T4 + D30T4 + D31T4 + D32T4 + D32T6 + D33T4 + D34T4 + D35T5 + D37T4 + D38T4
= T1+ (D1+ D2 + D3 + D4 + D10 + D14 + D22 + D24 + D27 + D29 + D30 + D31+ D32 + D33 + D34 + D37 + D38)T4 + D33T5 + (D4 + D32)T6
6. MBRin = T1+ D1T4 + D2T4 + D3T4 + D4T4 + D10T4 + D14T4 + D22T4 + D24T4 + D27T4 + D29T4 + D30T4 + D31T4 + D32T4 + D32T6 + D33T4 + D34T4 + D35T4 + D35T5 + D36T4 + D37T4 + D37T6 + D38T4
= T1+ (D1+ D2 + D3 + D4 + D10 + D14 + D22 + D24 + D27 + D29 + D30 + D31+ D32 + D33 + D34 + D35 + D36 + D37 + D38)T4 + D35T5 + (D32 + D37)T6
7. MBRout = T2 + D1T5 + D2T5 + D3T5 + D4T5 + D10T5 + D14T4 + D21T5 + D24T5 + D27T5 + D29T5 + D30T5*C + D31T5*Z + D32T5 + D32T7 + D33T5 + D34T5 + D36T5 + D37T7 + D37T7 + D38T6
= T2 + (D1+ D2 + D3 + D4 + D10 + D21+ D24 + D27 + D29 + D30*C + D31*Z + D32 + D33 + D34 + D36 + D37)T5 + D14T4 + D38T6 + (D32 + D37)T7
8. INin = T2
9. PCin = T2 + D1T4 + D2T4 + D3T4 + D4T4 + D10T4 + D14T4 + D22T4 + D24T4 + D27T4 + D30T5*C’ + D31T5*Z’ + D32T4 + D37T4 + D38T4
= T2 + (D1+ D2 + D3 + D4 + D10 + D14 + D22 + D24 + D27 + D32 + D37 + D38)T4 + (D30*C’ + D31*Z’)T5
10. Ain = D0T3 + D1T5 + D7T6 + D15T5 + D17T5 + D42T3 + D49T3
= (D0 + D42 + D49)T3 + (D1+ D15 + D17)T5 + D7T6
11. Aout = D7T3 + D8T3 + D11T3 + D12T3 + D15T3 + D17T3 + D19T3 + D22T3 + D25T3 + D35T3 + D40T4 + D47T3 + D48T6 + D49T3
= (D7 + D8 + D11+ D12 + D15 + D17 + D19 + D22 + D25 + D35 + D47 + D49)T3 + D40T4 + D48T6
12. Bin = D2T5 + D16T5 + D18T5 + D49T5
= (D2 + D16 + D18 + D49)T5
13. Bout = D0T3 + D7T4 + D9T3 + D11T4 + D13T3 + D16T3 + D18T3 + D20T3 + D22T3 + D26T3 + D34T3 + D36T3 + D41T4 + D47T4 + D49T4
= (D0 + D9 + D13 + D16 + D18 + D20 + D22 + D26 + D34 + D36)T3 + (D7 + D11+ D41+ D47 + D49)T4
14. ACin = D4T6 + D8T6 + D9T6 + D10T8 + D11T6 + D12T6 + D13T6 + D14T8 + D19T6 + D20T6 + D21T8 + D22T6 + D23T6 + D24T8 + D25T6 + D26T6 + D27T8 + D28T6 + D32T7 + D32T5 + D34T5 + D43T5 + D44T5 + D45T5 + D46T5 + D47T6
= (D32 + D34 + D43 + D44 + D45 + D46)T5 + (D4 + D8 + D9 + D11+ D12 + D13 + D19 + D20 + D22 + D23 + D25 + D26 + D28 + D47)T6 + D32T7 + (D10 + D14 + D21+ D24 + D27)T8
15. ACout = D3T6 + D8T4 + D9T4 + D10T6 + D12T4 + D13T4 + D14T6 + D19T4 + D20T4 + D21T6 + D22T4 + D23T4 + D24T6 + D25T4 + D26T4 + D27T6 + D28T3 + D35T4 + D36T4 + D37T6 + D43T3 + D44T3 + D45T3 + D46T3
= (D28 + D43 + D44 + D45 + D46)T3 + (D8 + D9 + D12 + D13 + D19 + D20 + D22 + D23 + D25 + D26 + D35 + D36)T4 + (D3 + D10 + D14 + D21+ D24 + D27 + D37)T6
16. MEMW = D3T6 + D36T5 + D37T7
17. PCdcr = D5T3
18. S0 = D15T4 + D16T4 + D17T4 + D18T4 + D25T5 + D26T5 + D27T7 + D28T4
= (D15 + D16 + D17 + D18 + D28)T4 + (D25 + D26)T5 + D27T7
19. S1 = D11T5 + D12T5 + D13T5 + D14T7 + D17T4 + D18T4 + D22T5 + D23T5 + D24T7 + D28T4 + D47T5
= (D17 + D18 + D28)T4 + (D11+ D12 + D13 + D22 + D23 + D47)T5 + (D14 + D24)T7
20. S2 = D19T5 + D20T5 + D21T7 + D22T5 + D23T5 + D24T7 + D25T5 + D26T5 + D27T7 + D28T4
= D28T4 + (D19 + D20 + D22 + D23 + D25 + D26)T5 + (D21+ D24 + D27)T7
21. Xin = D7T3 + D8T3 + D9T3 + D10T5 + D11T3 + D12T4 + D13T4 + D14T6 + D15T3 + D15T4 + D16T3 + D16T4 + D17T3 + D17T4 + D18T3 + D18T4 + D19T3 + D20T3 + D21T5 + D22T3 + D23T3 + D24T5 + D25T3 + D26T3 + D27T5 + D28T3 + D28T4 + D47T3 + D49T3
= (D7 + D8 + D9 + D11+ D15 + D16 + D17 + D18 + D19 + D20 + D22 + D23 + D25 + D26 + D28 + D47 + D49)T3 + (D12 + D13 + D15 + D16 + D17 + D18 + D28)T4 + (D10 + D21+ D24 + D27)T5 + D14T6
22. Xout = D15T5 + D16T5 + D17T5 + D18T5 + D28T5 + D49T5
= (D15 + D16 + 17 + D18 + D28 + D49)T5
23. Yin = D7T4 + D8T4 + D9T4 + D10T6 + D11T4 + D12T3 + D13T3 + D14T5 + D19T4 + D20T4 + D21T6 + D22T4 + D23T4 + D24T6 + D25T4 + D26T4 + D27T6 + D47T4
= (D12 + D13)T3 + (D7 + D8 + D9 + D11+ D19 + D20 + D22 + D23 + D25 + D26 + D47)T4 + (D10 + D21+ D24 + D27)T6
24. Cin = D11T3 + D12T3 + D13T3 + D14T5 + D15T3 + D16T3 + D47T3
= (D11+ D12 + D13 + D15 + D16 + D47)T3 + D14T5
25. Zin = D7T5 + D8T5 + D9T5 + D10T7 + D11T5 + D12T5 + D13T5 + D14T7 + D19T5 + D20T5 + D21T7 + D22T5 + D23T5 + D24T7 + D25T5 + D26T5 + D27T7 + D28T5 + D47T5
= (D7 + D8 + D9 + D11+ D12 + D13 + D19 + D20 + D22 + D23 + D25 + D26 + D28 + D47)T5 + (D10 + D14 + D21+ D24 + D27)T7
26. Zout = D7T6 + D8T6 + D9T6 + D10T8 + D11T6 + D13T6 + D14T8 + D19T6 + D20T6 + D21T8 + D22T6 + D23T6 + D25T6 + D26T6 + D27T8 + D28T6 + D47T6
= (D7 + D8 + D9 + D11+ D13 + D19 + D20D22 + D23 + D25 + D26 + D28 + D47)T6 + (D10 + D14 + D21+ D27)T8
27. SPWR = D38T5 + D40T4 + D41T4 + D48T4 + D48T6
= (D40 + D41+ D48)T4 + D38T5 + D48T6
28. SPRD = D39T3 + D42T3
= (D39 + D42)T3
29. SPinr = D39T4 + D42T4
= (D39 + D42)T4
30. SPdcr = D38T4 + D40T3 + D41T3 + D48T3 + D48T5
= (D40 + D41+ D48)T3 + D38T4 + D48T5
31. RL = D43T4 + D45T4
= (D43 + D45)T4
32. RR = D44T4 + D46T4
= (D44 + D46)T4
33. SRin = D43T3 + D44T3 + D45T3 + D46T3
= (D43 + D44 + D45 + D46)T3
34. SRout = D43T5 + D44T5 + D45T5 + D46T5
= (D43 + D44 + D45 + D46)T5
35. C = D45T3 + D46T3
= (D45 + D46)T3
36. FLagout = D48T4
Functions of Instructions
1. MOV A,B → Copies data from source register B to destination register A.
2. MVI A,data → Loads the data into the specified register A.
3. OUT 8-bit PORT ADDRESS → Sends the contents of the accumulator to the output port specified.
4. IN 8-bit PORT ADDRESS → Accepts data from the input port specified and loads into accumulator.
5. HLT → The address bus and data bus are placed in high impedance state.
6. NOP → No operation is performed.
7. ADD A,B → Adds the contents of registers A and B.
8. ADD A → Adds the contents of register A and accumulator.
9. ADI data → Adds the data to the contents of accumulator.
10. SUB A,B → Subtracts the contents of register B from the content of register A.
11. SUB A → Subtracts the contents of register A from the content of accumulator.
12. SUI data → Subtracts the data from the content of accumulator.
13. INR A → Increases the contents of register A by 1.
14. DCR A → Decreases the contents of register A by 1.
15. ANA A → Logically ANDs the contents of register A with the contents of the accumulator.
16. ANI data → Logically ANDs the data with the contents of the accumulator.
17. ORA A → Logically ORs the contents of register A with the contents of accumulator.
18. ORI data → Logically ORs the data with the contents of accumulator.
19. XRA A → Exclusive ORs the contents of register A with the contents of accumulator.
20. XRI data → Exclusive ORs the data with the contents of accumulator.
21. CMA → Complements the content of accumulator.
22. JMP 8-BIT ADDRESS → The program sequence is transferred to the memory location specified by the 8 bit address.
23. JC 8-BIT ADDRESS → Jump on carry.
24. JZ 8-BIT ADDRESS → Jump on zero.
25. LDA 8-bit ADDRESS → Load Accumulator direct i.e. copies the data from the memory location specified by 8-bit address into accumulator.
26. LDAX A → It copies the data byte from the memory location into the accumulator.
27. STAX A → It copies the data byte from accumulator into the memory location specified.
28. STA 8-bit ADDRESS → Store Accumulator direct i.e. copies data from the accumulator into the memory location specified by 8-bit address.
29. CALL 8-bit ADDRESS → Saves the contents of PC on stack by decrementing the SP register by 1 and jump unconditionally to the memory location specified.
30. RET → Inserts 1 byte from the top of the stack into the PC and increments the SP register by 1 and unconditionally return from a subroutine.
31. PUSH A → It copies the contents of register A on the stack.
32. POP A → It copies the contents of the top one memory location of the stack into the specified register A.
33. RLA → Rotate Accumulator left.
34. RRA → Rotate Accumulator right.
35. RLC → Rotate Accumulator left through carry.
36. RRC → Rotate Accumulator right through carry.
37. CMP A,B → The contents of the registers A and B are compared and result is kept in the accumulator.
38. PUSH PSW → The contents of accumulator and flag are copied to the stack.
39. XCHG A,B → Exchange the content of B with A.
The internal logic design of the microprocessor was a sequential process. With the completion of this design, we have become familiar with the internal architecture of microprocessor and the performance of each component that are used for design. We have tried to accumulate most of the instructions by writing their RTL, then function table and signal generation and finally preparing the block diagram of the microprocessor.
1 Ramesh Goankar, Microprocessor Architecture, Programming and Applications with the 8085, Fifth Edition
2 M. Morris Mano, Computer System Architecture, Third Edition
3 William Stalings, Computer Organization & Architecture, Sixth Edition