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A PROJECT REPORT ON DESIGN OF COMPUTER ARCHITECTURE

TRIBHUVAN UNIVERSITY
INSTITUTE OF ENGINEERING

Kathmandu Engineering College
Department of Electronics and Computer Engineering






A PROJECT REPORT ON DESIGN OF
COMPUTER ARCHITECTURE

PROJECT PROPOSAL SUBMITTED TO
THE DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR
THE BACHELOR OF ENGINEERING



SUBMITTED BY
1.
2.



Kathmandu, Nepal
26th April 2007

CONTENTS:

1.Acknowlegment 3
2.Abstract 4
3.Introduction 5
4Objective 5
5.Architectural Specification 6
6.Addressing mode 6
7.Hardware description 6
8.Instruction and coding 8
9.Classification of instruction 11
10.Functions of Instruction 12
11.Instruction used 14
12.RTL Design 20
13.Control unit Design 22
14.ALU design 24
15.Conclusion 27
16.Summary 28
17.Bibliography 28
18.Appendix 29











ACKNOWLEDGEMENT

A project of this proportion could not be completed without the assistance of some gracious people whom we must thank. We take this opportunity to express our sincere gratitude and indebtedness to our teacher Er. Pramod Poudel and Er. Raj Kumar Malla of Kathmandu Engineering College, Kalimati under whose guidance and encouragement, we could complete the project in given time frame. They have helped us by providing the certain field to explore and enhance our knowledge; which enhanced the ability to sustain in any circumstances and boost the capability of self-study and exploring the new development.

Our great sense of gratitude goes to all the peoples who have helped us directly and indirectly throughout the development of the project. Eventually, we sincerely appreciate meaningful suggestion and productive recommendation from individuals who go through this report.










ABSTRACT


This MICROPROCESSOR DESIGN has been done for the partial fulfillment of the fourth year first part of Bachelor’s Degree in Electronics and computer Engineering. We have achieved a clear idea about microprocessor with the help of this design-work. During the design, we faced lot of difficulties. No doubt, by this design work, we have got a lot of experiences.

By completing the design, we have got the complete knowledge about the internal architecture of microprocessor and the performance of each component that we have used for the design. Different operations can be achieved from microprocessor; we have tried to accumulate most of them by writing the required instructions and their RTL.

The design was a sequential process. First of all, we wrote the instructions we needed and their RTL, then function table and signal generation and finally the block diagram of microprocessor were designed.









1. INTRODUCTION
A microprocessor is a semiconductor device (integrated circuit) manufactured by using the LSI technique. It is a programmable digital device designed with registers, flip-flops and timing elements. The microprocessor has a set of instruction designed internally to manipulate data and communicate with peripherals. A microprocessor is regarded as a brain of PC and it performs all executing of instructions and processing of data. The processors may vary in their speed and capacity of memory, registers and data bus. An internal clock synchronizes and controls all the processor’s operations.

Regarding Processor, this microprocessor is capable of executing arithmetic and logical operations, memory read/ write operations and other some basic but fundamental tasks of a typical microprocessor.

1.1 OBJECTIVE OF THE PROJECT
To design a 8-bit Microprocessor Architecture Specification.

1.2 THE NAME OF THE TEAM MEMBERS
Suramya Sharma(716)
Sushil Acharya(718)

2. ARCHITECTURAL SPECIFICATIONS OF PROCESSOR
[2.1] Supports 20 instructions of Six categories viz. Data Transfer, Arithmetic,
[ 2 .2] Consists of three Addressing modes viz. Direct , Immediate and
Register direct addressing modes.
[2.3] Consists of two general purpose registers – B and A
[2.4] Consist of two flags – Z and Cy
.


3. ADDRESSING MODES
The Processor consists of four Addressing modes
[3.2.1] Direct Addressing mode – specify the effective address as part of
instruction
[3.2.2] Immediate Addressing mode – operand is specified in the instruction
itself
[3.2.3] Register Addressing mode – operand are in registers

4. HARDWARE DESCRIPTION OF PROCESSOR
The Processor is an Accumulator based 8-bit microprocessor that is intended to be used as a CPU in microcomputers. Its ALU, internal registers and its instructions are designed to work with 8-bit words. The Processor has 8-bit common data/address buses, so it can read data from or write data to memory 8–bit at a time and a control bus for providing timing signals to its various internal components.

The processor is constructed by means of MSI circuits such as registers, decoders, ALU, memory and multiplexers.

Hardware components of Processor :
REGISTERS
General Purpose Register
There is a general-purpose register viz. B that store 8 bit– data. It is user visible register and used for general operation .


Accumulator
It is a 8- bit register called that holds the 8-bit data for arithmetic and logical operations. The result of the operation is stored in it itself.

Program Counter ( PC )
This register points to the memory address from which next byte is to be fetched.

Stack pointer ( SP )
The 8 – bit stack pointer ( SP ) points to memory location in R/W memory called the stack. The beginning of the stack is defined by loading a 8 – bit address in the stack pointer.

The register Temp1 is user non visible register used for temporary storage for ALU operations.

MAR (Memory Address Register) holds the address of PC from where the instruction code is to be fetched.

MBR (Memory Buffer Register) temporarily holds the contents of memory specified by memory address register.

 IR (Instruction Register)
It holds the instruction codes of the instruction. It is an 8-bit register. Among the eight bits, bits 3,4 and 5 are used to select the decoder . Bits 0, 1 and 2 are used for inputs to the decoders that selects the instruction. The remaining bits 7 and 8 are not used so they have been set to 0.


The registers Temp1, MBR, MAR and IR transparent to the programmers i.e. programmer need not be concerned with them, because they are never referenced directly by any instructions. These registers are never used for storing data generated by one instruction for user by another instruction.

 INSTRUCTION DECODER
The Instruction decoder decodes the operation code so that processor knows what type of operation is to be performed before executing it.





ALU
The ALU is constructed with eight full-adder circuits connected in parallel as basic component. It is capable to support four different arithmetic operations, viz. Addition, Subtraction, Increment and Decrement and four logical operations AND, OR and XOR.

 CU
The CU (Control Unit) generates control signals for the processor. It provides the necessary timing and control signals to all the operations in the Processor. It is also responsible to control the flow of data between registers, memory and other components.

 CCU
The CCU (Code Converter Unit) is designed so to generate control signals for ALU.

BUS
There are two busses:
i. 8 – bit common address/data bus – to send out memory addresses and transfer data.
ii. A control bus – for timing signals

FLAGS
There are three flags viz. Z (Zero) and Cy (Carry). The flags simply work as status register. It has nothing to do with arithmetic and logic operation.

5. INSTRUCTIONS AND CODING
An ‘instruction’ is a binary pattern designed inside a microcomputer to perform a specific function. The entire group of instruction is called the ‘instruction set’ determines what function the microprocessor can perform.

5.1 INSTRUCTION CATEGORIES:
The 3S PROCESSOR consists of 20 instructions and can be classified into six
Categories:
5.1.1 Data Transfer
This category include the instructions (MOV, MVI, STAX, XCHG, LDA )that
transfer data from one location to another location. The data however is not
actually transferred but copied from one location to another.
5.1.2 Arithmetic
The instructions for arithmetic operations (ADD, SUB, INCREMENT,
DECREMENT) are included in this category.
5.1.3 Logical
The instructions for logical operations ( AND ,OR,XOR) are included in
this category.
5.1.4 Stack
The stack related instruction ( PUSH,POP)are included in this category.
5.1.5 Program Transfer
This category instructions (JMP,CALL)are related with transferring the
Program flow from one location to another.
5.1.6 Control Machine Instructions
The instruction in this category (HLT) maintains the flow of the Program.

The data-processing task with Processor can be altered simply by specifying a new program with different instructions or by specifying the same instructions with different data. Instruction codes, together with data, are stored in memory. An instruction code is a group of bits that tell the computer to perform a specific operation. The control reads each instruction from memory and places it in a Instruction register. The control then interpret the instruction and proceeds to execute it by issuing a sequence of control functions. The Processor has its own unique instruction repertoire. See APPENDIX for the instruction code and Hex code assignment for each instruction.

6. MEMORY CONTENT FOR A PROGRAM
The content of the Memory for particular set of instructions is shown in reference to the five operations when the processor executes following three instructions. The Hex code of these instructions is stored in memory locations from 01H to 06H as shown in figure.
01 0E MVI A, 40H
02 40
03 0D MOV A, B
04 02 ADD B

05 13 HLT
Note: The memory in the Processor is designed within it. In this section, the memory is shown outside the processor just to demonstrate the content of memory for particular set of instruction..











Classification of Instructions

According to function:
Data Transfer Arithmetic Logical Input/Output Transfer of Control
MOV A,B
MVI A, data
MVI B, data
LDA 8-bit ADDRESS
LDAX A
LDAX B
STAX A
STAX B
STA 8- bit ADDRESS
PUSH A
PUSH B
POP A
POP B
PUSH PSW
XCHG A, B ADD A,B
ADD A
ADD B
ADI data
SUB A,B
SUB A
SUB B
SUI data
INR A
INR B
DCR A
DCR B
ANA A
ANA B
ANI data
ORA A
ORA B
ORI data
XRA A
XRA B
XRI data
CMA
RLA
RRA
RLC
RRC
CMP A,B OUT 8- bit ADDRESS
IN 8- bit ADDRES HLT
NOP
JMP 8- bit ADDRESS
JC 8- bit ADDRESS
JZ 8- bit ADDRESS
CALL 8- bit ADDRESS
RET



According to Addressing Mode:
Direct Addressing Mode Stack Addressing Mode Immediate Addressing Mode Register Direct Addressing Mode Others
Out 8-bit PORT ADDRESS
In 8-bit PORT ADDRESS
JMP 8-bit ADDRESS
JC 8-bit ADDRESS
JZ 8-bit ADDRESS
LDA 8-bit ADDRESS
STA 8-bit ADDRESS
CALL 8-bit ADDRESS
RET PUSH A
PUSH B
POP A
POP PSW MVI A, data
MVI B, data
ADI data
SUI data
ANI data
ORI data
XRI data MOV A,B
ADD A,B
ADD A
ADD B
SUB A,B
SUB A
SUB B
INR A
INR B
DCR A
DCR B
ANA A
ANA B
ORA A
ORA B
XRA A
XRA B
CMP A,B
XCHG A,B HLT
NOP
CMA

Functions of Instructions

1. MOV A,B → Copies data from source register B to destination register A.
2. MVI A,data → Loads the data into the specified register A.
3. OUT 8-bit PORT ADDRESS → Sends the contents of the accumulator to the output port specified.
4. IN 8-bit PORT ADDRESS → Accepts data from the input port specified and loads into accumulator.
5. HLT → The address bus and data bus are placed in high impedance state.
6. NOP → No operation is performed.
7. ADD A,B → Adds the contents of registers A and B.
8. ADD A → Adds the contents of register A and accumulator.
9. ADI data → Adds the data to the contents of accumulator.
10. SUB A,B → Subtracts the contents of register B from the content of register A.
11. SUB A → Subtracts the contents of register A from the content of accumulator.
12. SUI data → Subtracts the data from the content of accumulator.
13. INR A → Increases the contents of register A by 1.
14. DCR A → Decreases the contents of register A by 1.
15. ANA A → Logically ANDs the contents of register A with the contents of the accumulator.
16. ANI data → Logically ANDs the data with the contents of the accumulator.
17. ORA A → Logically ORs the contents of register A with the contents of accumulator.
18. ORI data → Logically ORs the data with the contents of accumulator.
19. XRA A → Exclusive ORs the contents of register A with the contents of accumulator.
20. XRI data → Exclusive ORs the data with the contents of accumulator.

21. CMA → Complements the content of accumulator.
22. JMP 8-BIT ADDRESS → The program sequence is transferred to the memory location specified by the 8 bit address.
23. JC 8-BIT ADDRESS → Jump on carry.
24. JZ 8-BIT ADDRESS → Jump on zero.
25. LDA 8-bit ADDRESS → Load Accumulator direct i.e. copies the data from the memory location specified by 8-bit address into accumulator.
26. LDAX A → It copies the data byte from the memory location into the accumulator.
27. STAX A → It copies the data byte from accumulator into the memory location specified.
28. STA 8-bit ADDRESS → Store Accumulator direct i.e. copies data from the accumulator into the memory location specified by 8-bit address.
29. CALL 8-bit ADDRESS → Saves the contents of PC on stack by decrementing the SP register by 1 and jump unconditionally to the memory location specified.
30. RET → Inserts 1 byte from the top of the stack into the PC and increments the SP register by 1 and unconditionally return from a subroutine.
31. PUSH A → It copies the contents of register A on the stack.
32. POP A → It copies the contents of the top one memory location of the stack into the specified register A.
33. RLA → Rotate Accumulator left.
34. RRA → Rotate Accumulator right.
35. RLC → Rotate Accumulator left through carry.
36. RRC → Rotate Accumulator right through carry.
37. CMP A,B → The contents of the registers A and B are compared and result is kept in the accumulator.
38. PUSH PSW → The contents of accumulator and flag are copied to the stack.
39. XCHG A,B → Exchange the content of B with A.



INSTRUCTIONS USED IN OUR DESIGN:

ADDITION

1) ADD B: This will add the content of register B to the accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) + (B)
t5: AC ← (temp)
t 6: Reset

Similarly for ADD C
ADC D
ADD E

2) ADI 05H: This will add the data to the accumulator and store the results in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1
t6: temp ← (AC) + (MBR)
t7: AC ← temp
t 8: Reset


SUBTRACTION

3) SUB B: This will subtract the content of the register B from the accumulator and store the data in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) - (B)
t5: AC ← (temp)
t 6: Reset

4) SUI 21H: This will subtract the given data from the accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1
t6: temp ← (AC) - (MBR)
t7: AC ← temp
t 8: Reset

INCREMENT & DECREMENT

5) INR A: This will add one to the LSB of the accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) + 1
t5: AC ← (temp)
t 6: Reset

6) DCR A: This will subtract one from the LSB of the accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) - 1
t5: AC ← (temp)
t 6: Reset


LOGICAL INSTRUCTIONS

7) ANA B: This will logically AND the contents of a register B with the contents of accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) AND (B)
t5: AC ← (temp)
t 6: Reset

8) ORA C: This will logically OR the contents of the register C with the contents of accumulator and store the result in the accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) OR (C)
t5: AC ← (temp)
t 6: Reset

9) CMP B: -------------------------------------------------------------------------------------------------

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← CMP B
t5: AC ← (temp)
t 6: Reset


10) XRA M: This will logically Exclusive – OR the contents of the memory with the contents of accumulator and store the result back to the accumulator. The address of the memory is in HL register.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: temp ← (AC) XOR (M)
t5: AC ← (temp)
t 6: Reset

11) ANI FFH: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - -- - - - - - - - - - - - - - - - - - - - -

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)
t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1

t6: temp <--AND
t7: AC ← (temp)
t86: Reset


DATA TRANSFER INSTRUCTIONS

12) MOV A, B: This will move the data from the register B to accumulator.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: A ← (B)
t5: Reset

13) MOV B, A: This will move the data from the accumulator to register B.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: B ← (A)
t5: Reset

14) MOV B, C : This will move the data from the register C to register B.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: B ← (C)
t5: Reset


15) MVI A, 08H: This will load 8-bit data in register A.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1
t6: A ← (MBR)
t7: Reset

16) LDA 80H: This instruction copies the data byte into accumulator from the memory specified by 16 – bit address.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1
t6: MAR ← (MBR)
t7: MBR ← (Memory)
t 8: AC ← (MBR)
t 9: Reset

17) STA 20H: This instruction copies the data byte from accumulator into the memory specified by 16 – bit address.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
PC ← (PC) + 1
t6: MAR ← (MBR)
t7: MBR ← (AC)
t 8: (Memory ← (MBR)
t 9: Reset


BRANCH INSTRUCTION

18) JMP Address: This will shift the program counter to the value indicated by the data i.e. the instruction stored in the next address to jump instruction will not be called but instead the instruction in the memory indicated by the data will be called.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

t4: MAR ← (PC)
t5: MBR ← (Memory)
t6: PC ← (MBR)
t7: Reset

19) JC Address: This instruction changes the program sequence to the specified 8 – bit address if the carry flag is set.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

if C = 1 (carry flag set)
t4: MAR ← (PC)
t5: MBR ← (Memory)
t6: PC ← (MBR)
t7: Reset

else (carry flag not set i.e. C=0)

t4: PC ← (PC) + 1
t5: Reset


20) JZ Address: This instruction changes the program sequence to the specified 8 – bit address if the Zero flag is set.

t1: MAR ← (PC)
t2: MBR ← (Memory)
PC ← (PC) + 1
t3: IR ← (MBR)

if Z = 1 (Zero flag set)
t4: MAR ← (PC)
t5: MBR ← (Memory)
t6: PC ← (MBR)
t7: Reset

else (Zero flag not set i.e. Z=0)

t4: PC ← (PC) + 1
t5: Reset



7. RTL DESIGN

The Register Transfer Logic (RTL) is a convenient method for specifying the sequence of internal control functions in a digital computer, together with micro operation they execute. It will be shown now the design of RTL for the Processor as a convenient starting point for the design of the system.

In the Processor, the Program Counter (PC) holds the address of next instruction in memory. The PC goes through step by step counting sequence and causes the computer to read successive instructions previously stored in memory. To read an instruction, the content of PC are transferred into MAR and a memory read cycle initiated. The PC is then incremented by 1 so it holds the next address in the sequence of instructions. The operation code read from memory into MBR is then transferred into IR. If the memory address part of an instruction is read into MBR, this address is transferred into MAR to read the operand. Thus, MAR can receive address either from PC or from MBR.

Since the fetch cycle is common to all the instructions in the Processor, the RTL for fetch cycle of all the instruction is same. The fetch cycle of the instruction is described below and the RTL is shown next.

Fetch Cycle
1. In time T1, Program counter contains the address of the next instruction to be executed. The contents of program counter will be transferred to the memory address register(MAR). The memory address register then uses the address bus to transmit its contents, that specifies the address of memory location from where the instruction code is to be fetched.
2. When control unit issues the memory read signal, the content of the address memory location specified by MAR will be transferred to MBR. The T2 is the time period for this operation.
3. Finally the contents of MBR will be transferred to the instruction register(IR) and then the PC gets incremented. This happens in time T3.

T1: MAR<-PC
T2: MBR<-memory
T3: IR<-(MBR)
PC<-PC+1

Note: The contents of MBR can specify the address of the operands(if indirect addressing is used). Hence, the bracket( ) is included to indicate that its contents may not be the operand itself.

Execution Cycle:

The execution cycle for instruction LDA is explain in this section. The LDA (Load Accumulator Direct ) instruction copies the content of memory location specified by 8-bit address in the operand to the accumulator.
Example: LDA 02H

T4: MAR <- PC transfer next instruction address
T5: MBR <- M[MAR] read address, increment PC
: PC <- PC+1
T6: MAR <- MBR transfer operand address
T7: MBR <- M[MAR] read operand
T8: A <- MBR transfer operand to A, go to fetch cycle
: RST the sequence counter is cleared to zero.


At the end of execution each instruction, the sequence counter is cleared to zero so that the counter generates timing variable T1 to fetch next instruction.



8. THE INSTRUCTION DECODER DESIGN

The Instruction Decoder is basically a combination of seven 3 to 8 decoders which generates the 34 decoder signals. Among seven decoders, six of them are used to select the instructions and one decoder is used to select the six decoders.

9. CONTROL UNIT DESIGN

The CU (Control Unit ) generates control signals for the processor. It provides the necessary timing and control signals to all the operations in the Processor. It is also responsible to control the flow of data between registers, memory and other components.

The control unit receives the decoded signals from the instruction decoder and timing signal from sequence counter. Using this signal it generates the various control signals to carry out the various microinstructions.

The clock input to the CU is used to generate multiphase clock pulses that provide timing and control for internal functions. The clock is assumed to be available from the clock generator rather than from the processor itself.

The Sequence counter is decoded to supply eight timing variables T1 through T8. The counter is incremented with every clock pulse, but it can be cleared at any time to start a new sequence from T0

The timing counter starts from a value 0000000 which produces a T1 timing variable out of the decoder. The counter is incremented with every clock pulse and automatically produces the next timing variable in sequence. The first three timing variable is used for fetch cycle.
During timing variable T4, the operation code is in IR and one output of the instruction decoder is equal to 1.


The block diagram of the Control unit is shown below:



Figure 2 : Block diagram of Control Unit

9.1 SIGNALS GENERATED BY CU
9.1.1 ALU Signals:
The CU generates control signals for ALU operation.

9.1.2 Read , Write and Enable Signals:
The CU generates read/write, read, write signal and enable signals
depending upon various data operations. All signals are active high

9.1.3 Sequence counter Reset Signal

9.2 DESIGN CONCEPT OF CU
This section is dedicated to explain the design concept of Control Signal generation and Control Logic of Processor. For the sake of explanation, right now lets just consider three instructions and generate their corresponding control signals. This is a small instance of actual design discussed in this section in order to explain the design concept of CU. The actual design of CU of 3S-1G processor have been done using this concept.

Let us take now take one arithmetic instruction. Following table shows its corresponding Hex value, Decoder value, RTL and required control signals.
Table 1
S.no. Instruction Hex
code Decoder Value RTL Control Signals
1. ADD B 02 02 T4: Temp <- B+(A) Aout, B1out, Tempin
T5: A<-(Tem) Temp1out, Ain
T7: RST


10. THE ALU DESIGN

The ALU performs arithmetic and logical operations. It is a combinational circuit that has no internal storage. The basic component of arithmetic section of an ALU of the Processor is eight full-adder circuits connected in parallel. By controlling the data inputs to the parallel full-adders, four different types of arithmetic operations viz. ADD, SUB, INC and DEC are achieved.

The simplest and most straightforward design of a logic circuit is implemented in the ALU of the Processor. Since all logic operations can be obtained by means of AND and OR operations, the Processor has employed a logic circuit with just these operations. The exclusive-OR (XOR) functions has also been included in the design of logic circuit.

Figure 6 shows the block diagram of an 8-bit ALU with three bit status register (Flags).




Figure 6: Block Diagram of ALU


10.1 THE DESIGN OF ARITHMETIC CIRCUIT

The basic component of the arithmetic section of an ALU is parallel adder. A parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations. Figure 7 demonstrates the arithmetic operations obtained when one set of inputs to a parallel adder is controlled externally.
The input carry S0 goes to the full adder circuit in the least significant bit position. The output carry Cout comes from the full-adder circuit in the most significant bit position.







Figure 7. Operation obtained by controlling one set of inputs to a parallel adder.



Figure 9: One stage Arithmetic unit

Table 6
F0 F1 F2 Funtions
0 0 0 ADD
0 0 1 SUB
0 1 0 AND
0 1 1 OR
1 0 0 XOR


10.2 THE DESIGN OF LOGIC CIRCUIT

The logic micro operation manipulate the bits of the operands separately and treat each bit as a binary variable. Since all logic operations can be obtained by means of AND and OR operations, it may be more convenient to employ a logic circuit with just these operations. For three operations, we need two selection variables. But two selection lines can select among four logic operations, so we choose also the exclusive OR(XOR) function for the logic circuit designed. The simplest and most straightforward design of logic circuit is incorporated in Processor which is shown in sheet submitted.


Figure 10. One stage Logic Circuit

10.5 SETTING FLAGS OF ARITHMETIC AND LOGIC CIRCUIT


Figure 13: Setting Flag bits

The two flags bit are symbolized by Z, and Cy. The bits are set or cleared as a result of an operation performed in the ALU.

- Bit Z is set if the output of the ALU contains all 0’s and cleared otherwise. Z=1 if the result is zero and Z=0 if the result is nonzero.
- Bit Cy is set if the output carry of the ALU is 1. It is cleared if the output carry is 0.

12 CONCLUSION

Finally, our objective to design a 8-bit microprocessor Architecture seem to be achieved. We have designed a processor that is capable of processing 20 instructions of six different categories and three addressing modes.

In order to reduce complexity, we have used only one general purpose registers, though initially we had planned to include four. Nevertheless, the concept remains the same regardless of number of register used. We have used a common data/address bus to transfer data and address.
During the design process, we used most of our energy in making our design simple but logically correct. In other words, we focused on correctness rather than complexity. The designing process was commenced with careful selection of instructions and then vigilant composition of the RTL.

As far as external device interfacing with the processor is concerned, we have not included the instruction ( eg. IN, OUT) for it. SO, this can be regarded as a limitation to our Processor. Nevertheless, this limitation can be removed by undertaking few design modifications, but we choose not to do so in order to avoid circuit complication.

Eventually, this project on designing a processor has enabled us to understand the intricate aspect of microprocessor design. Apart from that, this project has compelled us to implement our past gained knowledge into practical work and hence reinforced our knowledge of standard microprocessors.

SUMMARY:
The internal logic design of the microprocessor was a sequential process.With the completion of this design we have become familiar with the internal architecture of microprocessor and the performance of each component that are used for design. We have tried to accumulate most of the instructions by writing their RTL,then function table and signal generation and finally preparing the block diagram of the microprocessor.


13 BIBLIOGRAPHY

 Last Name, First Name. “Title”. Publisher. Date of Publication.

 [1] Stallings, William. “Computer Organization and Architecture”.6th Edition.
 [2] Mano, M Morris. “Computer System Architecture”. Third Edition
 [3] Brey, B. Barry. “The Intel Microprocessor Architecture, Programming
and Interfacing.
 [4] Gaonkar, Ramesh. “Microprocessor Architecture, Programming and
Application with 8085. Fifth Edition.




APPENDIX
THE INSTRUCTION CODES
IR CONTENTS HEX CODE
S.No INSTRUCTIONS I7 I6 I5 I4 I3 I 2 I1 I0
1. MOV A,B 0 0 0 0 0 0 0 0 00
2. MOV B,A 0 0 0 0 0 0 0 1 01
3. MOV B,C 0 0 0 0 0 0 1 0 02
4. MVI A,08H 0 0 0 0 0 0 1 1 03
5. LDA 00H 0 0 0 0 0 1 0 0 04
6. STA 01H 0 0 0 0 0 1 0 1 05
7. ADD B 0 0 0 0 0 1 1 0 06
8. ADI 05H 0 0 0 0 0 1 1 1 07
9. SUB B 0 0 0 0 1 0 0 0 08
10. SUI 21H 0 0 0 0 1 0 0 1 09
11. INR A 0 0 0 0 1 0 1 0 0A
12. DCR A 0 0 0 0 1 0 1 1 0B
13. ANA B 0 0 0 0 1 1 0 0 0C
14. ORA C 0 0 0 0 1 1 0 1 0D
15. CMP B 0 0 0 0 1 1 1 0 0E
16. XRA B 0 0 0 0 1 1 1 1 0F
17. ANI FFH 0 0 0 1 0 0 0 0 10
18. JMP 01H 0 0 0 1 0 0 0 1 11
19. JC 01H 0 0 0 1 0 0 1 0 12
20. JZ 01H 0 0 0 1 0 0 1 1 13

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