Menu

Custom Search

A PROJECT REPORT ON DESIGN OF THE “3S-1G PROCESSOR”

TRIBHUVAN UNIVERSITY
INSTITUTE OF ENGINEERING

Kathmandu Engineering College
Department of Electronics and Computer Engineering






A PROJECT REPORT ON DESIGN OF
THE “3S-1G PROCESSOR”

PROJECT PROPOSAL SUBMITTED TO
THE DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR
THE BACHELOR OF ENGINEERING



SUBMITTED BY
1.
2.


Kathmandu, Nepal
April 2007



ACKNOWLEDGEMENT

It has always been a great excitement and fun undergoing the project of this standard which not only made us use our past gain knowledge into practical field but also taught us the value of time-factor and team work.

A project of this proportion could not be completed without the assistance of some gracious people whom we must thank. We take this opportunity to express our sincere gratitude and indebtedness to our teacher Er. Pramod Poudel and Er. Raj Kumar Malla of Kathmandu Engineering College, Kalimati under whose guidance and encouragement, we could complete the project in given time frame. They have helped us by providing the certain field to explore and enhance our knowledge; which enhanced the ability to sustain in any circumstances and boost the capability of self-study and exploring the new development.

Our great sense of gratitude goes to all the peoples who have helped us directly and indirectly throughout the development of the project. Eventually, we sincerely appreciate meaningful suggestion and productive recommendation from individuals who go through this report.







ABSTRACT

The 3S-1G Processor is an accumulator based 8-bit processor. It consists of an 8-bit common address/data bus, a control bus, two general-purpose registers, three Flags and four different addressing modes. The ALU is constructed with eight full-adder circuits connected in parallel as basic component and supports four different types of arithmetic operations and four logical operations. The processor includes 20 instructions of six functional categories: data transfer, arithmetic operations, logical operations, stack operation, program transfer operation and machine control operations. The Processor supports memory read and write operations and consist of one 8-bit Program Counter and one 8–bit Stack pointer.



















CONTENTS

1. INTRODUCTION 1
1.1 OBJECTIVE OF THE PROJECT 1
1.2 THE NAME OF THE TEAM MEMBERS 1
2. ARCHITECTURAL SPECIFICATIONS OF 3S-1G PROCESSOR 1
3. ADDRESSING MODES 2
4. HARDWARE DESCRIPTION OF 3S-1G PROCESSOR 2
5. INSTRUCTIONS AND CODING 5
5.1 INSTRUCTION CATEGORIES 5
6 MEMORY CONTENT FOR A PROGRAM 7
7 RTL DESIGN 8
8.THE INSTRUCTION DECODER DESIGN 10

9. CONTROL UNIT DESIGN 10
9.1 SIGNALS GENERATED BY CU 11
9.2 DESGN CONCEPT OF CU 12
10. THE ALU DESIGN 19
10.1 THE DESIGN OF ARITHMETIC CIRCUIT 20
10.2 THE DESIGN OF LOGIC CIRCUIT 22
10.3 THE DESIGN OF ARITHMETIC AND LOGIC CIRCUIT (ALU) 23
10.4 ONE STAGE ALU 24
10.5 SETTING FLAGS OF ARITHMETIC AND LOGIC CIRCUIT 25
11. DESIGN OF A CODE CONVERTER UNIT (CCU) 26

12 CONCLUDING REMARK 27

13 BIBLIOGRAPHY 28
APPENDIX A INSTRUCTION SETS 29
APPENDIX B RTL 31
APPENDIX C THE INSTRUCTION CODES 35
APPENDIX E TWO STAGE ALU 36
APPENDIX F DERIVATION OF CONTROL SIGNALS 37
1. INTRODUCTION
The 3S-1G Processor is an accumulator based 8-bit processor that has been designed as a semester project in partial fulfillment of the requirements for the Bachelor’s Degree in Computer Engineering.

A microprocessor is a semiconductor device (integrated circuit) manufactured by using the LSI technique. It is a programmable digital device designed with registers, flip-flops and timing elements. The microprocessor has a set of instruction designed internally to manipulate data and communicate with peripherals. A microprocessor is regarded as a brain of PC and it performs all executing of instructions and processing of data. The processors may vary in their speed and capacity of memory, registers and data bus. An internal clock synchronizes and controls all the processor’s operations.

Regarding 3S-1G Processor, this microprocessor is capable of executing arithmetic and logical operations, memory read/ write operations and other some basic but fundamental tasks of a typical microprocessor.

1.1 OBJECTIVE OF THE PROJECT
To design a 8-bit Microprocessor Architecture Specification.

1.2 THE NAME OF THE TEAM MEMBERS
[1.2.1] Subodh B.S. Thapa
[1.2.2] Subodh Nepal
[1.2.3] Suraj Pd. Dhungana
[1.2.4] Giri Raj Pandey

2. ARCHITECTURAL SPECIFICATIONS OF 3S-1G PROCESSOR
[2.1] Supports 20 instructions of Six categories viz. Data Transfer, Arithmetic,
Logical, Stack, Program Transfer and Control Machine Instructions.
[2.2] Consists of four Addressing modes viz. Direct , Immediate, Register and
Register indirect addressing modes.
[2.3] Consists of two general purpose registers – B and C.
[2.4] Consist of three flags – Z, Cy and S.
[2.5] Supports memory read and write operations.
[2.6] Consist of one 8-bit Program Counter and one 8–bit Stack pointer.

3. ADDRESSING MODES
The 3S-1G Processor consists of four Addressing modes
[3.2.1] Direct Addressing mode – specify the effective address as part of
instruction
[3.2.2] Immediate Addressing mode – operand is specified in the instruction
itself
[3.2.3] Register Addressing mode – operand are in registers
[3.2.4] Register indirect addressing modes – the instruction specifies a
register whose contents give the address of operand in the memory.

4. HARDWARE DESCRIPTION OF 3S-1G PROCESSOR
The 3S-1G Processor is an Accumulator based 8-bit microprocessor that is intended to be used as a CPU in microcomputers. Its ALU, internal registers and its instructions are designed to work with 8-bit words. The 3S-1G Processor has 8-bit common data/address buses, so it can read data from or write data to memory 8–bit at a time and a control bus for providing timing signals to its various internal components.

The 3S processor is constructed by means of MSI circuits such as registers, decoders, ALU, memory and multiplexers.

Hardware components of 3S-1G Processor :
REGISTERS
General Purpose Register
There are two general-purpose registers viz. B and C that store 8 bit– data. They are user visible register and are used for general operation .


Accumulator
It is a 8- bit register called that holds the 8-bit data for arithmetic and logical operations. The result of the operation is stored in it itself.

Program Counter ( PC )
This register points to the memory address from which next byte is to be fetched.

Stack pointer ( SP )
The 8 – bit stack pointer ( SP ) points to memory location in R/W memory called the stack. The beginning of the stack is defined by loading a 8 – bit address in the stack pointer.

Three registers Temp1, Temp2 and Temp3 are user non visible register used for temporary storage for ALU operations.

MAR (Memory Address Register) holds the address of PC from where the instruction code is to be fetched.

MBR (Memory Buffer Register) temporarily holds the contents of memory specified by memory address register.

 IR (Instruction Register)
It holds the instruction codes of the instruction. It is an 8-bit register. Among the eight bits, bits 3,4 and 5 are used to select the decoder . Bits 0, 1 and 2 are used for inputs to the decoders that selects the instruction. The remaining bits 7 and 8 are not used so they have been set to 0.
I7
I6
I5
I4 I3 I2 I1 I0

Unused bits



The registers Temp1, Temp2, Temp3, MBR, MAR and IR transparent to the programmers i.e. programmer need not be concerned with them, because they are never referenced directly by any instructions. These registers are never used for storing data generated by one instruction for user by another instruction.

 INSTRUCTION DECODER
The Instruction decoder decodes the operation code so that processor knows what type of operation is to be performed before executing it.

ALU
The ALU is constructed with eight full-adder circuits connected in parallel as basic component. It is capable to support four different arithmetic operations, viz. Addition, Subtraction, Increment and Decrement and four logical operations AND, OR, XOR and CMP (complement – NOT).

 CU
The CU (Control Unit) generates control signals for the processor. It provides the necessary timing and control signals to all the operations in the 3S-1G Processor. It is also responsible to control the flow of data between registers, memory and other components.

 CCU
The CCU (Code Converter Unit) is designed so to generate control signals for ALU.

BUS
There are two busses:
i. 8 – bit common address/data bus – to send out memory addresses and transfer data.
ii. A control bus – for timing signals

FLAGS
There are three flags viz. Z (Zero), Cy (Carry) and S (Sign). The flags simply work as status register. It has nothing to do with arithmetic and logic operation.

5. INSTRUCTIONS AND CODING
An ‘instruction’ is a binary pattern designed inside a microcomputer to perform a specific function. The entire group of instruction is called the ‘instruction set’ determines what function the microprocessor can perform.

5.1 INSTRUCTION CATEGORIES:
The 3S PROCESSOR consists of 20 instructions and can be classified into six
Categories:
5.1.1 Data Transfer
This category include the instructions (MOV, MVI, STAX, XCHG, LDA )that
transfer data from one location to another location. The data however is not
actually transferred but copied from one location to another.
5.1.2 Arithmetic
The instructions for arithmetic operations (ADD, SUB, NCREMENT,
DECREMENT) are included in this category.
5.1.3 Logical
The instructions for logical operations ( AND ,OR,XOR,CMP) are included in
this category.
5.1.4 Stack
The stack related instruction ( PUSH,POP)are included in this category.
5.1.5 Program Transfer
This category instructions (JMP,CALL,RET)are related with transferring the
Program flow from one location to another.
5.1.6 Control Machine Instructions
The instruction in this category (END, NOP) maintains the flow of the Program.

The data-processing task with 3S-1G Processor can be altered simply by specifying a new program with different instructions or by specifying the same instructions with different data. Instruction codes, together with data, are stored in memory. An instruction code is a group of bits that tell the computer to perform a specific operation. The control reads each instruction from memory and places it in a Instruction register. The control then interpret the instruction and proceeds to execute it by issuing a sequence of control functions. The 3S-1G Processor has its own unique instruction repertoire. See APPENDIX - C for the instruction code and Hex code assignment for each instruction.























6. MEMORY CONTENT FOR A PROGRAM

The content of the Memory for particular set of instructions is shown in reference to the five operations when the processor executes following three instructions. The Hex code of these instructions is stored in memory locations from 01H to 06H as shown in figure.

01 15 MVI B, 10H
02 10
03 16 MVI C,40H
04 40
05 10 MOV C
06 00 ADD B
07 20 END

Note: The memory in the 3S-1G Processor is designed within it. In this section, the memory is shown outside the processor just to demonstrate the content of memory for particular set of instruction..



7. RTL DESIGN

The Register Transfer Logic (RTL) is a convenient method for specifying the sequence of internal control functions in a digital computer, together with micro operation they execute. It will be shown now the design of RTL for the 3S-1G Processor as a convenient starting point for the design of the system.

In the 3S-1G Processor, the Program Counter (PC) holds the address of next instruction in memory. The PC goes through step by step counting sequence and causes the computer to read successive instructions previously stored in memory. To read an instruction, the content of PC are transferred into MAR and a memory read cycle initiated. The PC is then incremented by 1 so it holds the next address in the sequence of instructions. The operation code read from memory into MBR is then transferred into IR. If the memory address part of an instruction is read into MBR, this address is transferred into MAR to read the operand. Thus, MAR can receive address either from PC or from MBR.

Since the fetch cycle is common to all the instructions in the 3S-1G Processor, the RTL for fetch cycle of all the instruction is same. The fetch cycle of the instruction is described below and the RTL is shown next.

Fetch Cycle
1. In time T1, Program counter contains the address of the next instruction to be executed. The contents of program counter will be transferred to the memory address register(MAR). The memory address register then uses the address bus to transmit its contents, that specifies the address of memory location from where the instruction code is to be fetched.
2. When control unit issues the memory read signal, the content of the address memory location specified by MAR will be transferred to MBR. The T2 is the time period for this operation.
3. Finally the contents of MBR will be transferred to the instruction register(IR) and then the PC gets incremented. This happens in time T3.

T1: MAR<-PC
T2: MBR<-memory
T3: IR<-(MBR)
PC<-PC+1

Note: The contents of MBR can specify the address of the operands(if indirect addressing is used). Hence, the bracket( ) is included to indicate that its contents may not be the operand itself.

Execution Cycle:

The execution cycle for instruction LDA is explain in this section. The LDA (Load Accumulator Direct ) instruction copies the content of memory location specified by 8-bit address in the operand to the accumulator.
Example: LDA 02H

T4: MAR <- PC transfer next instruction address
T5: MBR <- M[MAR] read address, increment PC
: PC <- PC+1
T6: MAR <- MBR transfer operand address
T7: MBR <- M[MAR] read operand
T8: A <- MBR transfer operand to A, go to fetch cycle
: RST SC the sequence counter is cleared to zero.


At the end of execution each instruction, the sequence counter is cleared to zero so that the counter generates timing variable T1 to fetch next instruction.

The RTL of all the instruction is shown in APPENDIX – B


8.THE INSTRUCTION DECODER DESIGN

The Instruction Decoder is basically a combination of seven 3 to 8 decoders which generates the 34 decoder signals. Among seven decoders, six of them are used to select the instructions and one decoder is used to select the six decoders.

9. CONTROL UNIT DESIGN

The CU (Control Unit ) generates control signals for the processor. It provides the necessary timing and control signals to all the operations in the 3S-1G Processor. It is also responsible to control the flow of data between registers, memory and other components.

The control unit receives the decoded signals from the instruction decoder and timing signal from sequence counter. Using this signal it generates the various control signals to carry out the various microinstructions.

The clock input to the CU is used to generate multiphase clock pulses that provide timing and control for internal functions. The clock is assumed to be available from the clock generator rather than from the processor itself.

The Sequence counter is decoded to supply eight timing variables T1 through T8. The counter is incremented with every clock pulse, but it can be cleared at any time to start a new sequence from T0

The timing counter starts from a value 0000000 which produces a T1 timing variable out of the decoder. The counter is incremented with every clock pulse and automatically produces the next timing variable in sequence. The first three timing variable is used for fetch cycle.
During timing variable T4, the operation code is in IR and one output of the instruction decoder is equal to 1.


The block diagram of the Control unit is shown below:



Figure 2 : Block diagram of Control Unit

9.1 SIGNALS GENERATED BY CU
9.1.1 ALU Signals:
The CU generates eight control signals for ALU operation. They are
C3,C4,C5,C6,C7,C8,C9 and C10.

9.1.2 Read , Write and Enable Signals:
The CU generates read/write, read, write signal and enable signals
depending upon various data operations. The write signal is active low
signal, rest are active high.

9.1.3 Sequence counter Reset Signal

9.2 DESIGN CONCEPT OF CU
This section is dedicated to explain the design concept of Control Signal generation and Control Logic of 3S-1G Processor. For the sake of explanation, right now lets just consider three instructions and generate their corresponding control signals. This is a small instance of actual design discussed in this section in order to explain the design concept of CU. The actual design of CU of 3S processor have been done using this concept.

Let us take now take three instruction, one arithmetic instruction, one logic instruction and one data transfer instruction. Following table shows three instruction along with their corresponding Hex value, Decoder value, RTL and required control signals.
Table 1
S.no. Instruction Hex
code Decoder Value RTL Control Signals
1. ADD B 00 D0 T4: Temp1 <- A En A, Rd A, En Temp1,Wr Temp1
T5: Temp2<-B En B, Rd B, En Temp2, Wr Temp2
T6: Temp3<-Temp1+Temp2 ALU control signal, En Temp3,Wr Temp3
T7: A <- Temp3
RST SC En Temp3, Rd Temp3, En A, Wr A

2. AND B 01 D1 T4: Temp1 <- A En A, Rd A, En Temp1,Wr Temp1
T5: Temp2<-B En B, Rd B, En Temp2, Wr Temp2
T6: Temp3<-Temp1.Temp2 ALU control signal, En Temp3,Wr Temp3
T7: A <- Temp3
RST SC En Temp3, Rd Temp3, En A, Wr A

3. MOV B 02 D2 T4: A<-B
RST SC En B, Rd B, En A, Wr A

During time T4, the operation code is in IR and one output of the instruction decoder is equal to 1.

For instruction MOV B, it has decoder value D2. At T4, when D2 = 1, the content of B is copied to A.
Thus at T4D2 , A<- B is executed. With this concept, the microoperations for the three instruction are summarized below.

Table: 2

ADD B T4D0: Temp1 <- A
T5D0: Temp2<-B
T6D0: Temp3<-Temp1+Temp2
T7DO: A <- Temp3
RST SC

AND B T4D1: Temp1 <- A
T5D1: Temp2<-B
T6D1 Temp3<-Temp1.Temp2
T7D1 A <- Temp3
RST SC

MOV B T4D2: A<-B
RST SC


The first step in the design is to scan the register-transfer statements listed in Table 2 . and retrieve all those statements that perform the same microoperation on the same register. For example, the microperation Temp1 <- A is listed in the first line with control function T4D0 and in sixth line with control functionT4D1. The two lines are combined into one statement:
T4D0 + T4D1 : Temp1 <- A
A control function is a Boolean function. The + between the control functions denotes a Boolean OR operation, and the absence of an operator between T4 and D0 denotes a Boolean AND operation. The above statement combines all the control conditions for the transfer from A to Temp1. The control function can be manipulated as a Boolean function to give
C1 = T4(D0 +D1) : Temp1 <- A
There are seven different microoperation listed in Table 1. For each distinct microoperation, we accumulate the associated control functions and OR them together. The result is shown in Table 2.

Table 3: Hardware implementation

C1 = T4(D0+D1) Temp1 <- A
C2 = T5(D0+D1) Temp2<-B
C3 = T6D0 Temp3<-Temp1+Temp2
C4 = T6D1 Temp3<-Temp1.Temp2
C5 = T7(D0+D1) A <- Temp3
C6 = T4D2 A<-B
C7 = T7(D0+D1) + T4D2 RST SC
















Figure 3 shows the hardware implementation of Table 3


Figure 3 : Hardware implementation of Table 3

In Table 3, C3 and C4 are control signals to ALU that does addition and AND operation respectively. But C1,C2,C5 and C6 are control signals for register transfer operation. So, these signals are further modified in order to generate Enable, Read and Write signal.

In first line of Table 3, the value of A is being read and then copied to Temp1. So we need to enable register A and generate read signal to A. In fifth and sixth line, the value of Temp3 and B is copied to A respectively. So we need the enable A and generate write signal to it. This is summarized as
Ca A : C1 + C5’ + C6’
The write signal is active low so C5 and C6 are complemented.
Similarly other Control signals are summarized Table: 4




Table: 4

Cb = En A : C1 +C5 + C6
Cc = B : C2 + C6
Cd = En B : C2 + C6
Ce = Temp1: C1’+C3+C4
Cf = En Temp 1: C1+C3+C4
Cg = Temp 2: C2’+C3+C4
Ch = En Temp 2: C2+C3+C4
Ci = Temp3: C3’+C4’+C5
Cj = En Temp3: C3+C4+C5


Figure 4. shows the Hardware Implementation of Table 4.

Figure 4: Hardware implementation of Table 4
Now, lets look at what control signals are generated for particular instruction and how the instruction is executed. Suppose, the processor need to execute ADD B instruction. (see Table 1). For this, the Hex code of ADD B instruction which is 00 comes in IR at time T3. The IR send this code to Instruction Decoder for Decoding.
The Instruction Decoder then sends the decoded value of the instruction which is D0 to the control unit.



Now at time T4, the control unit generates an internal signal C1 ( to transfer content of A to Temp1) Figure 1. This c1 signal further generates signal Ca, Cb, Ce and Cf.Figure 2. The Cb enables the register A and control signal Ca sets register A into Read mode. Cf enables Temp1 and Ce set Temp1 in write mode. At this instant, the data of A is copied to Temp1.

At time T5, the control unit generates an internal signal c2( to transger content of b to Temp2) Figure 1.
This c2 signal further generates into signal Cc,Cd,Cg and Ch.Figure 2. The Cc enables the register B and control signal Cd sets register B into Read mode.Ch enables Temp2 and Cg set temp2 in write mode. At this instant the content of B is copied to Temp2.

At time T5, the control unit generates an external signal C3 ( The C3 is the control signal to ALU that add the contents of Temp 1 and Temp2 and stores the result in Temp3). The C3 signal further generates Ce,Cf,Cg,Ch,Ci and Cj signals. Here, Cf enable register Temp1,Ce sets Temp1 in read mode, Ch enables register Temp2, Cg set Temp2 in read mode,Cj enables Temp3 and Ci sets Temp3 in write mode.At this instant the result of addition within ALU comes at Temp3.

Now at Time T7, the CU generates signal C5 (to transfer content of Temp3 to register A).The signal C5 further generates signal Ca,Cb,Ci and Cj. Here again, Cb enables A,Ca sets A into write mode, Cj enables Temp3 and Ci sets Temp3 into read mode. At this instant, the content of Temp3 is transfered to A.
Now, the register A contains the value that is the sum of content of A and content of B.

The derivation of control unit signal of 3S Processor is shown in APPENDIX – F.




Figure 5: A small instance of Internal Circuitry of Control Unit of 3S PROCESSOR.

10. THE ALU DESIGN

The ALU performs arithmetic and logical operations. It is a combinational circuit that has no internal storage. The basic component of arithmetic section of an ALU of the 3S-1G Processor is eight full-adder circuits connected in parallel. By controlling the data inputs to the parallel full-adders, four different types of arithmetic operations viz. ADD, SUB, INC and DEC are achieved.

The simplest and most straightforward design of a logic circuit is implemented in the ALU of the 3S-1G Processor. Since all logic operations can be obtained by means of AND, OR and CMP ( complement) operations, the 3S-1G Processor has employed a logic circuit with just these operations. The exclusive-OR (XOR) functions has also been included in the design of logic circuit.

Figure 6 shows the block diagram of an 8-bit ALU with three bit status register (Flags).




Figure 6: Block Diagram of ALU


The eight data inputs from Temp1 are combined with the eight inputs from the Temp2 to generate an operation at Temp3 output.
The mode-select S3 distinguishes between arithmetic and logic operations. The two function select S2 and S1 specify the particular arithmetic or logic operation to be generated. With three selection variables ,it is possible t specify four arithmetic operations (with S2 in one state) and four logic operations (with S2 in other state).

The input carry in the least significant position of an ALU is quite often used as a fourth selection variable that can double the number of arithmetic operations. In this way, it is possible to generate four more operations, for a total of eight arithmetic operations.

The design of the ALU of 3S - 1G Processor is carried out in three stages. First, the design of the arithmetic section is undertake. Second, the design of the logic section is considered. Finally, the arithmetic section is modified so that it can perform both arithmetic and logic operations.

10.1 THE DESIGN OF ARITHMETIC CIRCUIT

The basic component of the arithmetic section of an ALU is parallel adder. A parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations. Figure 7 demonstrates the arithmetic operations obtained when one set of inputs to a parallel adder is controlled externally.
The input carry S0 goes to the full adder circuit in the least significant bit position. The output carry Cout comes from the full-adder circuit in the most significant bit position.







Figure 7. Operation obtained by controlling one set of inputs to a parallel adder.

The circuit that controls input to B to provide the functions illustrated in figure 7. is a true/complement, one/zero element. This circuit is illustrated in figure 8.



Figure 8: True/Complement, one/zero circuit
Table 5.
S2 S1 Bout
0 0 0
0 1 Bin
1 0 Bin’
1 1 1

The two selection lines S1 and S2 control the input of each B terminal.

A 1-bit arithmetic circuit that performs four arithmetic operation is shown in figure 9.The carry into the first stage is input carry and the carry out is the output carry. The selection variables are S0,S1 and S2. Variable S0 and S1 control all of the B inputs to the full adder circuits. The A input goes directly to the full adder.


Figure 9: One stage Arithmetic unit

Table 6
S2 S1 S0 Funtions
0 0 1 INC
0 1 0 ADD
1 0 1 SUB
1 1 0 DEC


10.2 THE DESIGN OF LOGIC CIRCUIT

The logic micro operation manipulate the bits of the operands separately and treat each bit as a binary variable. Since all logic operations can be obtained by means of AND,OR and CMP operations, it may be more convenient to employ a logic circuit with just these operations. For three operations, we need two selection variables. But two selection lines can select among four logic operations, so we choose also the exclusive OR(XOR) function for the logic circuit designed. The simplest and most straightforward design of logic circuit is incorporated in 3S-1G Processor which is shown in figure 10.


Figure 10. One stage Logic Circuit

Table 7

FUNCTION
S1 S0 Output Operation
0 X F = Temp1 + Temp 2 OR
1 X F = Temp 1 Temp2 XOR
0 X F = Temp1 . Temp2 AND
1 X F=Temp1` CMP


10.3 THE DESIGN OF ARITHMETIC AND LOGIC CIRCUIT (ALU)

Now, the arithmetic and logic circuit have been designed, we design arithmetic and logic circuit by modifying the arithmetic so that it can perform both arithmetic and logic operations. The block diagram of one stage ALU is shown in figure 11.



Figure 11: Block Diagram of One stage of Arithmetic Logic Unit
The design of an ALU is a combinational-logic problem. Because the unit has a regular pattern, it can be broken into identical stages connected in cascade through the carries. We designed one stage ALU and then duplicated it for the eight stages.
10.4 ONE STAGE ALU


Figure 12: One Stage Arithmetic Logic Unit

Table 8
Function selection Output FUNCTION
S¬3 S2 S1 S0
0 0 0 1 F = Temp + 1 INC Arithmetic
0 0 1 0 F = Temp1 + Temp 2 ADD
0 1 0 1 F = Temp 1 – Temp2 SUB
0 1 1 0 F = Temp1 – 1 DEC
1 0 0 x F = Temp1 + Temp 2 OR Logical
1 0 1 x F = Temp 1 Temp2 XOR
1 1 0 x F = Temp1 . Temp2 AND
1 1 1 x F=Temp1` CMP



10.5 SETTING FLAGS OF ARITHMETIC AND LOGIC CIRCUIT


Figure 13: Setting Flag bits

The three flags bit are symbolized by Z, S and Cy. The bits are set or cleared as a result of an operation performed in the ALU.

- Bit Z is set if the output of the ALU contains all 0’s and cleared otherwise. Z=1 if the result is zero and Z=0 if the result is nonzero.
- Bit S is set if the MSB of the result in the output of the ALU (the sign bit) is 1. It is cleared if the MSB is 0.
- Bit Cy is set if the output carry of the ALU is 1. It is cleared if the output carry is 0.









11. DESIGN OF A CODE CONVERTER UNIT (CCU)

A code converter circuit is basically an encoder circuit which is designed so as to generate four control signals (viz. S0,S1,S2 and S3) of ALU. It has eight inputs signal from the Control Unit and the four output signals. These four output signals are the control signals for ALU. In simple words, the Control Unit generates eight signal for ALU operation and these eight signals is converted into Four signal by Code Converter Unit .
Following table shows the Truth Table for the “Code Converter Circuit.”

TRUTH TABLE
¬¬¬¬
Operations Control
Signal C3 C4 C5 C6 C7 C8 C9 C10 S3 S2 S1 S0
INCREMENT C5 0 0 1 0 0 0 0 0 0 0 0 1
ADDITION C3 1 0 0 0 0 0 0 0 0 0 1 0
SUBTRACTION C4 0 1 0 0 0 0 0 0 0 1 0 1
DECREMENT C6 0 0 0 1 0 0 0 0 0 1 1 0
OR C8 0 0 0 0 0 1 0 0 1 0 0 0
XOR C9 0 0 0 0 0 0 1 0 1 0 1 0
AND C7 0 0 0 0 1 0 0 0 1 1 0 0
CMP C10 0 0 0 0 0 0 0 1 1 1 1 0

Derivation of ALU control Signal

S0 = C5 + C4
S1 = C3 + C6 + C9 + C10
S2 = C4 + C6 + C7 + C10
S3 = C8 + C9 + C7 + C10













12 CONCLUDING REMARK

Finally, our objective to design a 8-bit microprocessor Architecture seem to be achieved. We have designed a processor that is capable of processing 20 instructions of six different categories and four addressing modes.

In order to reduce complexity, we have used only two general purpose registers, though initially we had planned to include six. Nevertheless, the concept remains the same regardless of number of register used. We have used a common data/address bus to transfer data and address.

During the design process, we used most of our energy in making our design simple but logically correct. In other words, we focused on correctness rather than complexity. The designing process was commenced with careful selection of instructions and then vigilant composition of the RTL.

While designing ALU, we were more concerned in circuit reduction. Thus we modified the full adder circuit so that it can perform other arithmetic instruction without loosing its effectiveness. Since we hadn't included any conditional instruction, so utilizing the content of flags was not on our focus.

In case of CU design, we have generated the control signals excluding the fetch cycle ie. after the instruction comes into IR. We have employed hardwired control unit though we realized the nuisance that would be created when we have to make change in one instructions but again the hardwired CU proved to be much faster to design than microprogrammed.

As far as external device interfacing with the processor is concerned, we have not included the instruction ( eg. IN, OUT) for it. SO, this can be regarded as a limitation to our Processor. Nevertheless, this limitation can be removed by undertaking few design modifications, but we choose not to do so in order to avoid circuit complication.

Eventually, this project on designing a processor has enabled us to understand the intricate aspect of microprocessor design. Apart from that, this project has compelled us to implement our past gained knowledge into practical work and hence reinforced our knowledge of a standard microprocessors.



13 BIBLIOGRAPHY

 [1] Last Name, First Name. “Title”. Publisher. Date of Publication.
 [1] Stallings, William. “Computer Organization and Architecture”.6th Edition.
 [2] Mano, M Morris. “Computer System Architecture”. Third Edition
 [3] Brey, B. Barry. “The Intel Microprocessor Architecture, Programming
and Interfacing.
 [4] Gaonkar, Ramesh. “Microprocessor Architecture, Programming and
Application with 8085. Fifth Edition.




















APPENDIX A
INSTRUCTION SETS
S.No. Operation Opcode Operand No. of
Bytes Description
[A] ARITHMETIC
1. ADD R* 1 Adds content of register to the content of A & stores the result in A.
2. SUB R* 1 Subtracts the content of register to the content of A & stores the result in A.
3. INC R* 1 Increase the content of register by 1.
4. DEC R* 1 Decrease the content of register by 1.
[B] LOGICAL
5. AND R* 1 Logically ANDs the contents of register with content of A and store the result in A.
6. OR R* 1 Logically ORs the contents of register with content of A and store the result in A.
7. XOR R* 1 Logically Exclusive ORs the contents of register with content of A and store the result in A.
8. CMP A 1 Complements the bits of Accumulator.
[C] DATA TRANSFER
9. MOV Rd,Rs* 1 Copies data from source register to destination register.
10.. MVI R*,Data
2 Loads 8-bits of into the specified register.
11. LDA Address 2 Load Accumulator Direct. The content of memory location specified by 8-bit address in the operand are copied to the accumulator. Example: LDA 02H.
12. STAX None 1 Contents of Accumulator are copied into memory location specified by the registers B or C.
13. XCHG None 1 The contents of register B are exchanged with the contents of register C.
[D] STACK OPERATION
14. PUSH None 1 The contents of A are copied to memory location pointed by SP
15. POP None 1 The contents of memory location pointed by SP is copied to A
[E] PROGRAM TRANSFER
16. JMP Address 2 Jump to Program Control unconditionally.
17. CALL Address 2 Jump to Program Control conditionally.

18. RET None 1 Jump to Program Control after completing the subroutine.
[F] CONTROL MACHINE
19. END None 1 Clears PC.
20. NOP None 1 No operation is performed. The instruction is fetched and decoded however no operation is executed.




















APPENDIX B
RTL
S.No. Operations Instructions Decoder
Value RTL
[A] ARITHMETIC
1.




































ADD
a. ADD B D0 T4: Temp1<-A
T5: Temp2<-B
T6:Temp3<-Temp1+Temp2
T7: A<-Temp3
: RST SC

b.
ADD C D1 T4: Temp1<-A
T5: Temp2<-C
T6: Temp3<-Temp1+Temp2
T7: A<-Temp3
: RST SC
2. SUB
a. SUB B D2 T4: Temp1<-A
T5: Temp2<-B
T6: Temp3<-Temp1-Temp2
T7: A<-Temp3
: RST SC

b. SUB C D3 T4: Temp1<-A
T5: Temp2<-C
T6: Temp3<-Temp1-Temp2
T7: A<-Temp3
: RST SC
3 INC
a. INC B D4 T4: A<-B
T5: TEMP1<-A
T6: TEMP3<- TEMP1 + 1
T7: A<- Temp3
T8: B<- A
: RST SC

b. INC C D5 T4: A<-C
T5: TEMP1<-A
T6: TEMP3<- TEMP1 + 1
T7: A<- Temp3
T8: C<- A
: RST SC
4. DEC
a. DEC B D6 T4: A<-B
T5: TEMP1<-A
T6: TEMP3<- TEMP1 - 1
T7: A<- Temp3
T8: B<- A
: RST SC

b. DEC C D7 T4: A<-C
T5: TEMP1<-A
T6: TEMP3<- TEMP1 - 1
T7: A<- Temp3
T8: C<- A
: RST SC
[B] LOGICAL
5.



AND
a.


AND B


D8 T4: Temp1<-A
T5: Temp2<-B
T6: Temp3<-Temp1.*Temp2
T7: A<-Temp3
: RST SC

b. AND C D9 T4: Temp1<-A
T5: Temp2<-C
T6: Temp3<-Temp1.*Temp2
T7: A<-Temp3
: RST SC
6. OR
a. OR B D10 T4: Temp1<-A
T5: Temp2<-B
T6: Temp3<-Temp1+*Temp2
T7: A<-Temp3
: RST SC

b. OR C D11 T4: Temp1<-A
T5: Temp2<-C
T6: Temp3<-Temp1+*Temp2
T7: A<-Temp3
: RST SC
7. XOR
a. XOR B D12 T4: Temp1<-A
T5: Temp2<-B
T6: Temp3<-Temp1ÄTemp2
T7: A<-Temp3
: RST SC

b. XOR C D13 T4: Temp1<-A
T5: Temp2<-C
T6:Temp3<-Temp1ÄTemp2
T7: A<-Temp3
: RST SC

8. CMP D14 T4: Temp1<-A
T5: Temp3<-Temp1’
T6: A<-Temp3
: RST SC
[C] DATA TRANSFER
9.





MOV

a. MOV B D15 T4: A<-B
: RST SC


b. MOV C D16 T4: A<-C
: RST SC


c. MOV B,A D17 T4: A<-B
: RST SC

d. MOV C,A D18 T4: C<-A
: RST SC

e. MOV B,C D19 T4: B<-C
: RST SC

f. MOV C,B D20 T4: C<-B
: RST SC
10. MVI
a. MVI B,data D21 T4: MAR <- PC
T5: MBR <- M[MAR]
T6: B <- MBR
: PC <- PC+1
: RST SC

b. MVI C, data D22 T4: MAR <- PC
T5: MBR <- M[MAR]
T6: C <- MBR
: PC <- PC+1
: RST SC

11. LDA D23 T4: MAR <- PC
T5: MBR <- M[MAR]
: PC <- PC+1
T6: MAR <- MBR
T7: MBR <- M[MAR]
T8: A <- MBR
: RST SC
12. STAX
a. STAX B D24 T4: MBR <- A
T5: MAR <- B
T6: M[MAR] <- MBR
: RST SC

b. STAX C D25 T4: MBR <- A
T5: MAR <- C
T6: M[MAR] <- MBR
: RST SC

13. XCHG D26 T4: A<- B
T5: B<- C
T6: C<- A
: RST SC
[D] STACK OPERATION
14.




PUSH D27 T4: MBR <- A
SP <- SP + 1
T5: MAR <- SP
T6: M[MAR] <- MBR
: RST SC

15.
POP
D28 T4: MAR <- SP
T5: MBR <- M[MAR]
SP <- SP -1
T6: A <- MBR
: RST SC
[E] PROGRAM TRANSFER
16. JMP address D29 T4: MAR <- PC
T5: PC <- M[MAR]
: PC <- PC+1
: RST SC

17. CALL address D30 T4: SP <- PC
: SP <- SP +1
T5: MAR <- PC
T6: PC <- M[MAR]
: PC <- PC + 1
: RST SC

18. RET D31 T4: MAR <- SP
: SP <- SP-1
T5: PC <- M[MAR]
: PC <- PC +1
: RST SC

[F] CONTROL MACHINE
19. END D32 T4: RST SC

20. NOP D33 T4: -


sc : Sequence Counter
Ä XOR
.* AND
+* OR











APPENDIX C
THE INSTRUCTION CODES
IR CONTENTS HEX CODE DECODER
VALUE
S.No OPERATIONS INSTRUCTIONS I7 I6 I5 I4 I3 I 2 I1 I0
1. Arithmetic ADD B 0 0 0 0 0 0 0 0 00 D0
2. ADD C 0 0 0 0 0 0 0 1 01 D1
3. SUB B 0 0 0 0 0 0 1 0 02 D2
4. SUB C 0 0 0 0 0 0 1 1 03 D3
5. INC B 0 0 0 0 0 1 0 0 04 D4
6. INC C 0 0 0 0 0 1 0 1 05 D5
7. DEC B 0 0 0 0 0 1 1 0 06 D6
8. DEC C 0 0 0 0 0 1 1 1 07 D7
9. Logical AND B 0 0 0 0 1 0 0 0 08 D8
10. AND C 0 0 0 0 1 0 0 1 09 D9
11. OR B 0 0 0 0 1 0 1 0 0A D10
12. OR C 0 0 0 0 1 0 1 1 0B D11
13. XOR B 0 0 0 0 1 1 0 0 0C D12
14. XOR C 0 0 0 0 1 1 0 1 0D D13
15. CMP 0 0 0 0 1 1 1 0 0E D14
16. Data Transfer MOV B 0 0 0 0 1 1 1 1 0F D15
17. MOV C 0 0 0 1 0 0 0 0 10 D16
18. MOV B,A 0 0 0 1 0 0 0 1 11 D17
19. MOV C,A 0 0 0 1 0 0 1 0 12 D18
20. MOV B,C 0 0 0 1 0 0 1 1 13 D19
21. MOV C,B 0 0 0 1 0 1 0 0 14 D20
22. MVI B,DATA 0 0 0 1 0 1 0 1 15 D21
23. MVI C,DATA 0 0 0 1 0 1 1 0 16 D22
24. LDA ADDRESS 0 0 0 1 0 1 1 1 17 D23
25. STAX B 0 0 0 1 1 0 0 0 18 D24
26. STAX C 0 0 0 1 1 0 0 1 19 D25
27. XCHG 0 0 0 1 1 0 1 0 1A D26
28. Stack
Operation PUSH 0 0 0 1 1 0 1 1 1B D27
29. POP 0 0 0 1 1 1 0 0 1C D28
30. Program
Transfer JUMP 0 0 0 1 1 1 0 1 1D D29
31. CALL 0 0 1 1 1 1 1 0 1E D30
32. RET 0 0 1 1 1 1 1 1 1F D31
33. Control
Machine END 0 0 1 0 0 0 0 0 20 D32
34 NOP 0 0 1 0 0 0 0 1 21 D33





APPENDIX E

TWO STAGE ALU

APPENDIX F

DERIVATION OF CONTROL SIGNALS

Control Signal internal to CU

S.No. Signal Operation Expression
1. C1 TEMP1 <- A T4(D0+D1+D2+D3+D8+D9+D10+D11+D12+D13+D14) + T5(D4+D5+D6+D7)
2. C2 TEMP2 <- B T5(D0+D2+D8+D10+D12)
3. C11 A <- TEMP3 T7(D0+D1+D2+D3+D4+D5+D6+D7+D8+D9+D10+D11+D12+D13+D14)
4. C12 TEMP2 <- C T5(D1+D3+D9+D11+D13)
5. C13 A <- B T4(D4+D6+D15+D17+D26)
6. C14 A <- C T4(D5+D7+D16)
7. C15 B <- A T8(D4+D6)
8. C16 C <- A T8(D5+D7)+T4D18+T6D26
9. C17 B <- C T4D19+T5D26
10. C18 C <- B T4D20
11. C19 MAR <- PC T4(D21+D22+D23+D29)+T5D30
12. C20 MBR <- M[MAR] T5(D21+D22+D23+D28)+T7D23
13. C21 B <- MBR T6D21
14.
C22 PC <- PC +1 T6(D21+D22+D30)+T5(D23+D29+D31)
15. C23 C <- MBR T6D22
16. C24 MAR <- MBR T6D23
17. C25 MBR <- A T4(D24+D25+D27)
18. C26 M[MAR] <- MBR T6(D24+D25+D27)
19. C27 MAR <- B T5D24
20. C28 A <- MBR T6D28+T8D23
21. C29 MAR <- C T5D25
22. C30 SP <- SP+1 T5d27+T4D30
23. C31 MAR <- SP T5D27+T4(D28+D31)
24. C32 PC <-M[MAR] T6D30+T5(D29+D31)
25. C33 SP <- PC T4D30
26. C34 SP <- SP – 1 T5D28+T4D31
27. C35 RST SC T4(D15+D16+D17+D18+D19+D20+D32)+T5(D29+D31)+ T6(D14+D21+D22+D24+D25+D26+D27+D28+D30)+T7(D0+D1+D2+D3+D8+D9+D10+D11+D12+D13)+T8(D4+D5+D6+ D7+D23)





Control Signal external to CU

S.No. Signal Operation Expression
1. C3 TEMP3<-TEMP1+TEMP2 T6(D0+D1)
2. C4 TEMP3<-TEMP1-TEMP2 T6(D2+D3)
3. C5 TEMP3<-TEMP1+1 T6(D4+D5)
4. C6 TEMP3<-TEMP1-1 T6(D6+D7)
5. C7 TEMP3<-TEMP1.*TEMP2 T6(D8+D9)
6. C8 TEMP3<-TEMP1+*TEMP2 T6(D10+D11)
7. C9 TEMP3<-TEMP1ÄTEMP2 T6(D12+D13)
8. C10 TEMP3<-TEMP1’ T5D14
9. Ca A
C1+C11’+C12’+C13’+C14+C15+C16+C25+C28’
10. Cb En A C1+C11+C12+C13+C14+C15+C16+C25+C28
11. Cc Temp1
C1’
12. Cd En Temp1 C1
13. Ce Temp2
C2’
14. Cf En Temp2 C2
15. Cg RD Temp3 C11
16. Ch En Temp3 C11
17. Ci B
C13+C15’+C17’+C18+C21’+C27
18. Cj En B C13+C14+C17+C18+C21+C27
19. Ck C
C12+C14’+C16+C17+C18’+C23’+C29
20. Cl En C C12+C14+C16+C17+C18+C23+C29
21. Cm MAR
C19’+C20+C24+C26+C27’+C29’+C31’+C32
22. Cn En MAR C19+C20+C24+C26+C27+C29+C31+C32
23. Co MBR
C20’+C21+C23+C24+C25’+C26+C28
24. Cp En MBR C20+C21+C23+C24+C25+C26+C28
25. Cq M (Memory)
C20+C26’+C32
26. Cr En M C20+C26+C32
27. Cs PC
C19+C32’+C33
28. Ct En PC C19+C32+C33
29. Cu SP
C31+C33’
30. Cv En SP C31+C33
31. Cw En Increment address latch C22+C31
32. Cx En Decrement Address Latch C34








CODE CONVERTER UNIT [CCU]

No comments:

Post a Comment